Investigating Impact of Bit-flip Errors in Control Electronics on Quantum Computation

Subrata Das, Avimita Chatterjee, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we investigate the impact of bit-flip errors in FPGA memories in control electronics on quantum computing systems. FPGA memories are integral in storing the amplitude and phase information pulse envelopes, which are essential for generating quantum gate pulses. However, these memories can incur faults due to physical and environmental stressors such as electromagnetic interference, power fluctuations, and temperature variations and adversarial fault injections, potentially leading to errors in quantum gate operations. To understand how these faults affect quantum computations, we conducted a series of experiments to introduce bit flips into the amplitude (both real and imaginary components) and phase values of quantum pulses using IBM's simulated quantum environments, FakeValencia, FakeManila, and FakeLima. We compare the sensitivity of floating-point and fixed-point representations to these bit-flip errors. The findings reveal that bit flips in the exponent and initial mantissa bits of the real amplitude in floating- point representation cause substantial deviations in quantum gate operations, with TVD increases as high as 200%. Conversely, fixed-point representation shows reduced sensitivity to bit-flips, offering a more robust alternative for certain applications. These in- sights can guide the selection of data representations to enhance the robustness of quantum computing systems from hardware faults.

Original languageEnglish (US)
Title of host publicationProceedings - 38th International Conference on VLSI Design, VLSID 2025 - held concurrently with 24th International Conference on Embedded Systems, ES 2025
PublisherIEEE Computer Society
Pages558-563
Number of pages6
ISBN (Electronic)9798331522445
DOIs
StatePublished - 2025
Event38th International Conference on VLSI Design, VLSID 2025 - Bengaluru, India
Duration: Jan 4 2025Jan 8 2025

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Conference

Conference38th International Conference on VLSI Design, VLSID 2025
Country/TerritoryIndia
CityBengaluru
Period1/4/251/8/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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