TY - GEN
T1 - Investigating simple low latency reliable multiported register files
AU - Ricketts, Andrew J.
AU - Mutyam, Madhu
AU - Vijaykrishnan, N.
AU - Irwin, Mary Jane
PY - 2007
Y1 - 2007
N2 - Multiport register files are a key component in the design and operation of high performance microprocessors. Due to the frequency of accesses of these register files per clock cycle errors manifested here can potentially spread rapidly. This can seriously compromise the validity of data and even system reliability. Errors may be caused from any number of possible sources including radiation induced soft errors, read or write errors, and permanent device errors. This work focuses on combating errors that affect a stored entry in a register file, but our techniques can often also detect and recover from many other potential sources of errors. Up to 4 bit errors are detectable with 6.25% storage overhead over an unprotected register file. The recovery for most types of errors requires in the order of a few nanoseconds and requires 4% less energy than a monolithic register file with comparable characteristics but no error protection.
AB - Multiport register files are a key component in the design and operation of high performance microprocessors. Due to the frequency of accesses of these register files per clock cycle errors manifested here can potentially spread rapidly. This can seriously compromise the validity of data and even system reliability. Errors may be caused from any number of possible sources including radiation induced soft errors, read or write errors, and permanent device errors. This work focuses on combating errors that affect a stored entry in a register file, but our techniques can often also detect and recover from many other potential sources of errors. Up to 4 bit errors are detectable with 6.25% storage overhead over an unprotected register file. The recovery for most types of errors requires in the order of a few nanoseconds and requires 4% less energy than a monolithic register file with comparable characteristics but no error protection.
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U2 - 10.1109/ISVLSI.2007.62
DO - 10.1109/ISVLSI.2007.62
M3 - Conference contribution
AN - SCOPUS:36348931468
SN - 0769528961
SN - 9780769528960
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures
SP - 375
EP - 380
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI
T2 - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Y2 - 9 March 2007 through 11 March 2007
ER -