TY - GEN
T1 - Investigation of InxGa1-xAs FinFET architecture with varying indium (x) concentration and quantum confinement
AU - Arun, Vt
AU - Agrawal, Nidhi
AU - Lavallee, Guy
AU - Cantoro, Mirco
AU - Kim, Sang Su
AU - Kim, Dong Won
AU - Datta, Suman
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/9/8
Y1 - 2014/9/8
N2 - InxGa1-xAs FinFETs with varying indium percentage, x, and vertical body thicknesses, are fabricated in a closely packed fin configuration (10 fins per micron of layout area) and their relative performance analyzed and benchmarked. In0.7Ga0.3As quantum well FinFET (QWFF) exhibits peak field effect mobility of 3,000 cm2/V-sec at a fin width of 38nm with highest performance. Short channel In0.7Ga0.3As QWFF (Lg=120nm) exhibits IDSAT of 1.16mA/μm at VG-VT=1V and extrinsic peak gm=1.9mS/μm at VDS=0.5V and IOFF=30 nA/μm. Components of external resistance (RExt), side wall DIT, fin profile are analyzed to investigate feasibility of InxGa1-xAs FinFET for beyond 10nm technology node.
AB - InxGa1-xAs FinFETs with varying indium percentage, x, and vertical body thicknesses, are fabricated in a closely packed fin configuration (10 fins per micron of layout area) and their relative performance analyzed and benchmarked. In0.7Ga0.3As quantum well FinFET (QWFF) exhibits peak field effect mobility of 3,000 cm2/V-sec at a fin width of 38nm with highest performance. Short channel In0.7Ga0.3As QWFF (Lg=120nm) exhibits IDSAT of 1.16mA/μm at VG-VT=1V and extrinsic peak gm=1.9mS/μm at VDS=0.5V and IOFF=30 nA/μm. Components of external resistance (RExt), side wall DIT, fin profile are analyzed to investigate feasibility of InxGa1-xAs FinFET for beyond 10nm technology node.
UR - http://www.scopus.com/inward/record.url?scp=84907681097&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84907681097&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2014.6894372
DO - 10.1109/VLSIT.2014.6894372
M3 - Conference contribution
AN - SCOPUS:84907681097
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - Digest of Technical Papers - Symposium on VLSI Technology
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th Symposium on VLSI Technology, VLSIT 2014
Y2 - 9 June 2014 through 12 June 2014
ER -