TY - GEN
T1 - Large-body-sized Glass-based Active Interposer for High-Performance Computing
AU - Ravichandran, Siddharth
AU - Kathaperumal, Mohanalingam
AU - Swaminathan, Madhavan
AU - Tummala, Rao
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - This paper presents a next generation glass-based active interposer with 2 micron polymer RDL. Passive 2.5D interposers have become a mainstream solution to address the bandwidth demands of high-performance computing (HPC) applications. However, such passive interposers face challenges in meeting future performance, cost and reliability needs and active interposers have been studied recently as a means of scaling interposer performance. Given the ability to grow CMOS on Silicon more readily, only Silicon has been studied as substrate core for active interposers. However, for large body sizes, Silicon is not cost effective and interconnects tend to be lossy over long distances. Glass has been explored as a passive interposer core previously, and glass-based panel embedding (GPE) solutions have also been developed for fanout applications. This work uses GPE technology to demonstrate a glass-based active interposer substrate with potential for large-body-sized packages. The key challenge, however, in achieving a wiring density of over 250 IO/mm is the surface non-coplanarities associated with cavities in glass substrates. This paper describes the fabrication process for a Glass-based active interposer with dies embedded in glass cavities, and a systematic parametric process optimization to improve the surface planarity to demonstrate 2 micron L/S RDL on die-embedded glass substrates.
AB - This paper presents a next generation glass-based active interposer with 2 micron polymer RDL. Passive 2.5D interposers have become a mainstream solution to address the bandwidth demands of high-performance computing (HPC) applications. However, such passive interposers face challenges in meeting future performance, cost and reliability needs and active interposers have been studied recently as a means of scaling interposer performance. Given the ability to grow CMOS on Silicon more readily, only Silicon has been studied as substrate core for active interposers. However, for large body sizes, Silicon is not cost effective and interconnects tend to be lossy over long distances. Glass has been explored as a passive interposer core previously, and glass-based panel embedding (GPE) solutions have also been developed for fanout applications. This work uses GPE technology to demonstrate a glass-based active interposer substrate with potential for large-body-sized packages. The key challenge, however, in achieving a wiring density of over 250 IO/mm is the surface non-coplanarities associated with cavities in glass substrates. This paper describes the fabrication process for a Glass-based active interposer with dies embedded in glass cavities, and a systematic parametric process optimization to improve the surface planarity to demonstrate 2 micron L/S RDL on die-embedded glass substrates.
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U2 - 10.1109/ECTC32862.2020.00144
DO - 10.1109/ECTC32862.2020.00144
M3 - Conference contribution
AN - SCOPUS:85090265684
T3 - Proceedings - Electronic Components and Technology Conference
SP - 879
EP - 884
BT - Proceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 70th IEEE Electronic Components and Technology Conference, ECTC 2020
Y2 - 3 June 2020 through 30 June 2020
ER -