TY - GEN
T1 - Lattice priority scheduling
T2 - 22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016
AU - Ferraiuolo, Andrew
AU - Wang, Yao
AU - Zhang, Danfeng
AU - Myers, Andrew C.
AU - Suh, G. Edward
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/4/1
Y1 - 2016/4/1
N2 - Computer hardware is increasingly shared by distrusting parties in platforms such as commercial clouds and web servers. Though hardware sharing is critical for performance and efficiency, this sharing creates timing-channel vulnerabilities in hardware components such as memory controllers and shared memory. Past work on timing-channel protection for memory controllers assumes all parties are mutually distrusting and require timing-channel protection. This assumption limits the capability of the memory controller to allocate resources effectively, and causes severe performance penalties. Further, the assumption that all entities are mutually distrusting is often a poor fit for the security needs of real systems. Often, some entities do not require timing-channel protection or trust others with information. We propose lattice priority scheduling (LPS), a secure memory scheduling algorithm that improves performance by more precisely meeting the target system's security requirements, expressed as a lattice policy. We evaluate LPS in a simulated 8-core microprocessor. Compared to prior solutions [34], lattice priority scheduling improves system throughput by over 30% on average and by up to 84% for some workloads.
AB - Computer hardware is increasingly shared by distrusting parties in platforms such as commercial clouds and web servers. Though hardware sharing is critical for performance and efficiency, this sharing creates timing-channel vulnerabilities in hardware components such as memory controllers and shared memory. Past work on timing-channel protection for memory controllers assumes all parties are mutually distrusting and require timing-channel protection. This assumption limits the capability of the memory controller to allocate resources effectively, and causes severe performance penalties. Further, the assumption that all entities are mutually distrusting is often a poor fit for the security needs of real systems. Often, some entities do not require timing-channel protection or trust others with information. We propose lattice priority scheduling (LPS), a secure memory scheduling algorithm that improves performance by more precisely meeting the target system's security requirements, expressed as a lattice policy. We evaluate LPS in a simulated 8-core microprocessor. Compared to prior solutions [34], lattice priority scheduling improves system throughput by over 30% on average and by up to 84% for some workloads.
UR - http://www.scopus.com/inward/record.url?scp=84965032107&partnerID=8YFLogxK
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U2 - 10.1109/HPCA.2016.7446080
DO - 10.1109/HPCA.2016.7446080
M3 - Conference contribution
AN - SCOPUS:84965032107
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 382
EP - 393
BT - Proceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016
PB - IEEE Computer Society
Y2 - 12 March 2016 through 16 March 2016
ER -