Leakage-aware compilation for VLIW architectures

W. Zhang, Y. F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units.

Original languageEnglish (US)
Pages (from-to)251-260
Number of pages10
JournalIEE Proceedings: Computers and Digital Techniques
Issue number2
StatePublished - Mar 2005

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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