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Leakage-aware compilation for VLIW architectures
W. Zhang
, Y. F. Tsai
,
M. Kandemir
,
N. Vijaykrishnan
, M. J. Irwin
, V. De
School of Electrical Engineering and Computer Science
Institute for Computational and Data Sciences (ICDS)
Computer Science and Engineering
Research output
:
Contribution to journal
›
Article
›
peer-review
2
Scopus citations
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Keyphrases
Chip Design
50%
Compiler
100%
Compiler-based
50%
Data Flow Analysis
50%
EnergyPlus Software
50%
Fabrication Methods
50%
Leakage Current
50%
Leakage Energy
50%
Leakage Power
50%
Media Applications
50%
Power Consumption
50%
Set-reset
50%
Simulation Environment
50%
Software Design
50%
Threshold Voltage
50%
Transistor
50%
Computer Science
Data-Flow Analysis
33%
Experimental Result
33%
Functional Unit
100%
Instruction Word
100%
Leakage Current
33%
Power Consumption
100%
Simulation Environment
33%
Software Design
33%
Static Power
33%
Threshold Voltage
33%