TY - GEN
T1 - Leakage-aware interconnect for on-chip network
AU - Tsai, Yuh Fang
AU - Narayaynan, Vijaykrishnan
AU - Xie, Yuan
AU - Irwin, Mary Jane
PY - 2005
Y1 - 2005
N2 - On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.
AB - On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.
UR - http://www.scopus.com/inward/record.url?scp=33646945055&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33646945055&partnerID=8YFLogxK
U2 - 10.1109/DATE.2005.195
DO - 10.1109/DATE.2005.195
M3 - Conference contribution
AN - SCOPUS:33646945055
SN - 0769522882
SN - 0769522882
SN - 9780769522883
T3 - Proceedings -Design, Automation and Test in Europe, DATE '05
SP - 230
EP - 231
BT - Proceedings - Design, Automation and Test in Europe, DATE '05
T2 - Design, Automation and Test in Europe, DATE '05
Y2 - 7 March 2005 through 11 March 2005
ER -