Leakage-aware interconnect for on-chip network

Yuh Fang Tsai; Vijaykrishnan Narayaynan; Yuan Xie; Mary Jane Irwin

doi:10.1109/DATE.2005.195

Leakage-aware interconnect for on-chip network

Yuh Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

Original language	English (US)
Title of host publication	Proceedings - Design, Automation and Test in Europe, DATE '05
Pages	230-231
Number of pages	2
DOIs	https://doi.org/10.1109/DATE.2005.195
State	Published - 2005
Event	Design, Automation and Test in Europe, DATE '05 - Munich, Germany Duration: Mar 7 2005 → Mar 11 2005

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE '05
Volume	I
ISSN (Print)	1530-1591

Other

Other	Design, Automation and Test in Europe, DATE '05
Country/Territory	Germany
City	Munich
Period	3/7/05 → 3/11/05

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/DATE.2005.195

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title = "Leakage-aware interconnect for on-chip network",

abstract = "On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.",

author = "Tsai, {Yuh Fang} and Vijaykrishnan Narayaynan and Yuan Xie and Irwin, {Mary Jane}",

year = "2005",

doi = "10.1109/DATE.2005.195",

language = "English (US)",

isbn = "0769522882",

series = "Proceedings -Design, Automation and Test in Europe, DATE '05",

pages = "230--231",

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note = "Design, Automation and Test in Europe, DATE '05 ; Conference date: 07-03-2005 Through 11-03-2005",

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TY - GEN

T1 - Leakage-aware interconnect for on-chip network

AU - Tsai, Yuh Fang

AU - Narayaynan, Vijaykrishnan

AU - Xie, Yuan

AU - Irwin, Mary Jane

PY - 2005

Y1 - 2005

N2 - On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

AB - On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes .Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

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U2 - 10.1109/DATE.2005.195

DO - 10.1109/DATE.2005.195

M3 - Conference contribution

AN - SCOPUS:33646945055

SN - 0769522882

SN - 9780769522883

T3 - Proceedings -Design, Automation and Test in Europe, DATE '05

SP - 230

EP - 231

BT - Proceedings - Design, Automation and Test in Europe, DATE '05

T2 - Design, Automation and Test in Europe, DATE '05

Y2 - 7 March 2005 through 11 March 2005

ER -

Leakage-aware interconnect for on-chip network

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