Leakage optimized DECAP design for FPGAs

On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associated with it and is estimated to increase with technology scaling. A recent work has proposed a gated decap structure to reduce leakage in decaps. Their work analyzes leakage saving obtained by implementing gated decap structure in a pipelined super scalar core. FPGAs on the otherhand face similar leakage problem associated with decaps in their unmapped regions. We analyze here the leakage saving due to gated decap structure in FPGAs. With the on-chip gated decap structure we do uniform placement of decaps that achieves decap leakage savings of 7-60% with 39% on an average for various MCNC benchmarks mapped on to the FPGA device.