Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs

Prasanth Mangalagiri; Vijaykrishnan Narayanan

doi:10.1109/ISVLSI.2009.42

Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs

Prasanth Mangalagiri, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design flow that will increase the average life-time of components by ensuring uniform aging. We first study the impact of temperature and voltage variations on lifetime reliability of components. In the presence of such variations, we study the impact of aging in FPGA interconnects due to Electromigration (EM), and di-electric breakdown due to Time Dependent Dielectric Breakdown (TDDB). We also consider the performance degradation due to Hot Carrier Instability (HCI) in our design flow optimizations. The proposed reliability aware design flow techniques achieve an average of 65.8% and 75% improvement in lifetime of LUTs and interconnect wires respectively.

Original language	English (US)
Title of host publication	Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Pages	61-66
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2009.42
State	Published - 2009
Event	2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 - Tampa, FL, United States Duration: May 14 2009 → May 15 2009

Publication series

Name	Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Other

Other	2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Country/Territory	United States
City	Tampa, FL
Period	5/14/09 → 5/15/09

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2009.42

Cite this

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title = "Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs",

abstract = "Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design flow that will increase the average life-time of components by ensuring uniform aging. We first study the impact of temperature and voltage variations on lifetime reliability of components. In the presence of such variations, we study the impact of aging in FPGA interconnects due to Electromigration (EM), and di-electric breakdown due to Time Dependent Dielectric Breakdown (TDDB). We also consider the performance degradation due to Hot Carrier Instability (HCI) in our design flow optimizations. The proposed reliability aware design flow techniques achieve an average of 65.8% and 75% improvement in lifetime of LUTs and interconnect wires respectively.",

author = "Prasanth Mangalagiri and Vijaykrishnan Narayanan",

year = "2009",

doi = "10.1109/ISVLSI.2009.42",

language = "English (US)",

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series = "Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009",

pages = "61--66",

booktitle = "Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009",

note = "2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 ; Conference date: 14-05-2009 Through 15-05-2009",

}

Mangalagiri, P & Narayanan, V 2009, Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs. in Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009., 5076384, Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp. 61-66, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, Tampa, FL, United States, 5/14/09. https://doi.org/10.1109/ISVLSI.2009.42

Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs. / Mangalagiri, Prasanth; Narayanan, Vijaykrishnan.
Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009. 2009. p. 61-66 5076384 (Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs

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