TY - GEN
T1 - Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
AU - Marongiu, Andrea
AU - Benini, Luca
AU - Kandemir, Mahmut
N1 - Funding Information:
This work has been partially supported by Universidad de Guadalajara (UdG), Mexican institution, and National (MEC) and Madrid (CAM) Spanish institutions under the following projects: 60789 and 76817 (UdG), PTFNN (MEC ref: AGL2006-12689/AGR), CES3D (CAM ref: CCG07-UPM/AMB-1998) and GASC/UPM (CAM ref: CCG07-UPM/000-1995).
PY - 2007
Y1 - 2007
N2 - Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is barrier instructions which are used to perform global synchronization across parallel processors. This scenario calls for a lightweight synchronization infrastructure. In this work we describe a lightweight barrier support library for a non-cache-coherent MPSoC architecture. The library is coupled with a parallelizing compiler front-end to set up a complete automated flow which, starting from a sequential code, produces the parallelized binary code that can be directly executed onto an MPSoC target (a multi-core non-cache-coherent ARM7 platform). This tool-flow has been characterized in terms of system performance and energy.
AB - Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is barrier instructions which are used to perform global synchronization across parallel processors. This scenario calls for a lightweight synchronization infrastructure. In this work we describe a lightweight barrier support library for a non-cache-coherent MPSoC architecture. The library is coupled with a parallelizing compiler front-end to set up a complete automated flow which, starting from a sequential code, produces the parallelized binary code that can be directly executed onto an MPSoC target (a multi-core non-cache-coherent ARM7 platform). This tool-flow has been characterized in terms of system performance and energy.
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U2 - 10.1145/1289881.1289908
DO - 10.1145/1289881.1289908
M3 - Conference contribution
AN - SCOPUS:38849129910
SN - 9781595938268
T3 - CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
SP - 145
EP - 149
BT - CASES'07
T2 - CASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Y2 - 30 September 2007 through 3 October 2007
ER -