Logic Synthesis for Field-Programmable Gate Arrays

Ting Ting Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo Hua Wang

Research output: Contribution to journalArticlepeer-review

21 Scopus citations


In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA‘s) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices.

Original languageEnglish (US)
Pages (from-to)1280-1287
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number10
StatePublished - Oct 1994

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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