Low-leakage robust SRAM cell design for sub-100nm technologies

Keyphrases

• Soft Error 100%
• Low Leakage 100%
• SRAM Cell 100%
• Gate Dielectric 66%
• Leakage Power 66%
• Gate Leakage 66%
• Subthreshold Leakage Current 66%
• SRAM Design 66%
• Transistor 33%
• Field-induced 33%
• Capacitance 33%
• Bitline 33%
• 6T-SRAM 33%
• Cutout 33%
• Circuit Level 33%
• Transistor Circuits 33%
• HSPICE 33%
• Reliability Degree 33%
• Fringing Field 33%
• Novel Hybrids 33%
• Leakage Error 33%

Engineering

• Soft Error 100%
• Cell Design 100%
• Gate Dielectric 66%
• Nodes 33%

Immunology and Microbiology

• Electric Potential 100%