TY - GEN
T1 - Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
AU - Ghosh, Swaroop
AU - Bhunia, Swarup
AU - Roy, Kaushik
PY - 2007
Y1 - 2007
N2 - Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, frequency scaling, simultaneous voltage-frequency tuning etc. increase the design complexity and/or degrade the performance significantly. In this paper, we propose a novel design technique, which makes a circuit amenable to temperature adaptation using dynamic voltage scheduling (DVS). It is accomplished by a synthesis technique that (a) isolates and predicts the set of paths that may become critical under variations, (b) ensures they are activated rarely, and (c) tolerates possible delay failures (at reduced voltage) in these paths by adaptive clock stretching. This allows us to schedule a lower supply voltage during increased temperature without requiring frequency tuning. Simulation results on an example pipeline show that proposed design yields similar temperature reduction as conventional design with only 11% performance penalty and 14% area overhead. The conventional pipeline design, on contrary, leads to 50% performance degradation due to reduced operating frequency.
AB - Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, frequency scaling, simultaneous voltage-frequency tuning etc. increase the design complexity and/or degrade the performance significantly. In this paper, we propose a novel design technique, which makes a circuit amenable to temperature adaptation using dynamic voltage scheduling (DVS). It is accomplished by a synthesis technique that (a) isolates and predicts the set of paths that may become critical under variations, (b) ensures they are activated rarely, and (c) tolerates possible delay failures (at reduced voltage) in these paths by adaptive clock stretching. This allows us to schedule a lower supply voltage during increased temperature without requiring frequency tuning. Simulation results on an example pipeline show that proposed design yields similar temperature reduction as conventional design with only 11% performance penalty and 14% area overhead. The conventional pipeline design, on contrary, leads to 50% performance degradation due to reduced operating frequency.
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U2 - 10.1109/DATE.2007.364518
DO - 10.1109/DATE.2007.364518
M3 - Conference contribution
AN - SCOPUS:34548361450
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1532
EP - 1537
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -