Low-power and process variation tolerant memories in sub-90nm technologies

Saibal Mukhopadhyay; Swaroop Ghosh; Keejortg Kim; Kaushik Roy

doi:10.1109/SOCC.2006.283871

Low-power and process variation tolerant memories in sub-90nm technologies

Saibal Mukhopadhyay, Swaroop Ghosh, Keejortg Kim, Kaushik Roy

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-seale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self-repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub-90nm technologies.

Original language	English (US)
Title of host publication	2006 IEEE International Systems-on-Chip Conference, SOC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	155-159
Number of pages	5
ISBN (Print)	0780397819, 9780780397811
DOIs	https://doi.org/10.1109/SOCC.2006.283871
State	Published - Jan 1 2006
Event	2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States Duration: Sep 24 2006 → Sep 27 2006

Publication series

Name	2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other	2006 IEEE International Systems-on-Chip Conference, SOC
Country/Territory	United States
City	Austin, TX
Period	9/24/06 → 9/27/06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2006.283871

Cite this

Mukhopadhyay, S., Ghosh, S., Kim, K., & Roy, K. (2006). Low-power and process variation tolerant memories in sub-90nm technologies. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 155-159). Article 4063040 (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283871

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title = "Low-power and process variation tolerant memories in sub-90nm technologies",

abstract = "Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-seale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self-repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub-90nm technologies.",

author = "Saibal Mukhopadhyay and Swaroop Ghosh and Keejortg Kim and Kaushik Roy",

year = "2006",

month = jan,

day = "1",

doi = "10.1109/SOCC.2006.283871",

language = "English (US)",

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series = "2006 IEEE International Systems-on-Chip Conference, SOC",

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Mukhopadhyay, S, Ghosh, S, Kim, K & Roy, K 2006, Low-power and process variation tolerant memories in sub-90nm technologies. in 2006 IEEE International Systems-on-Chip Conference, SOC., 4063040, 2006 IEEE International Systems-on-Chip Conference, SOC, Institute of Electrical and Electronics Engineers Inc., pp. 155-159, 2006 IEEE International Systems-on-Chip Conference, SOC, Austin, TX, United States, 9/24/06. https://doi.org/10.1109/SOCC.2006.283871

Low-power and process variation tolerant memories in sub-90nm technologies. / Mukhopadhyay, Saibal; Ghosh, Swaroop; Kim, Keejortg et al.
2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc., 2006. p. 155-159 4063040 (2006 IEEE International Systems-on-Chip Conference, SOC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Low-power and process variation tolerant memories in sub-90nm technologies

AU - Mukhopadhyay, Saibal

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AU - Roy, Kaushik

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N2 - Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-seale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self-repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub-90nm technologies.

AB - Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-seale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self-repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub-90nm technologies.

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T3 - 2006 IEEE International Systems-on-Chip Conference, SOC

SP - 155

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BT - 2006 IEEE International Systems-on-Chip Conference, SOC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE International Systems-on-Chip Conference, SOC

Y2 - 24 September 2006 through 27 September 2006

ER -

Low-power and process variation tolerant memories in sub-90nm technologies

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All Science Journal Classification (ASJC) codes

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