Convolution serves as the basic computational primitive for various associative computing tasks ranging from edge detection to image matching. CMOS implementation of such computations entails significant bottlenecks in area and energy consumption due to the large number of multiplication and addition operations involved. In this paper, we propose an ultra-low power and compact hybrid spintronic-CMOS design for the convolution computing unit. Low-voltage operation of domain-wall motion based magneto-metallic "Spin-Memristor"s interfaced with CMOS circuits is able to perform the convolution operation with reasonable accuracy. Simulation results of Gabor filtering for edge detection reveal ∼ 2.5× lower energy consumption compared to a baseline 45nm-CMOS implementation.
|Title of host publication
|Proceedings of the 53rd Annual Design Automation Conference, DAC 2016
|Institute of Electrical and Electronics Engineers Inc.
|Published - Jun 5 2016
|53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
Duration: Jun 5 2016 → Jun 9 2016
|Proceedings - Design Automation Conference
|53rd Annual ACM IEEE Design Automation Conference, DAC 2016
|6/5/16 → 6/9/16
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation