Abstract
A multi-level carry-skip addition scheme for static CMOS is presented which has O(lg n) asymptotic delay and has speed comparable to a carry-lookahead approach for typical operand bit precisions. However, the proposed architecture results in adders which dissipate nearly half the power of carry-lookahead adders. The proposed carry-skip method is also conflict free. This paper describes the proposed architecture and its circuit implementation, as well as the architecture's asymptotic worst case delay analysis. Also, empirical results comparing the adder's performance with other conventional architectures in a 0.5 μm CMOS process are provided.
| Original language | English (US) |
|---|---|
| Pages | 87-90 |
| Number of pages | 4 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) - Ames, IA, USA Duration: Aug 18 1996 → Aug 21 1996 |
Other
| Other | Proceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) |
|---|---|
| City | Ames, IA, USA |
| Period | 8/18/96 → 8/21/96 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering