Abstract
This article discusses some design considerations in building deeply pipelined FIR filters using CMOS technology. The impact of these considerations on the area, speed and power dissipation of FIR filters is elaborated. Furthermore, detailed HOSPICE simulation results are presented to illustrate the relative power dissipations of the different approaches.
Original language | English (US) |
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Pages | 32-33 |
Number of pages | 2 |
State | Published - 1995 |
Event | Proceedings of the 1995 IEEE Symposium on Low Power Electronics - San Jose, CA, USA Duration: Oct 9 1995 → Oct 11 1995 |
Other
Other | Proceedings of the 1995 IEEE Symposium on Low Power Electronics |
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City | San Jose, CA, USA |
Period | 10/9/95 → 10/11/95 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials