TY - GEN
T1 - Low-power high-speed current mode logic using Tunnel-FETs
AU - Tsai, Wei Yu
AU - Liu, Huichu
AU - Li, Xueqing
AU - Narayanan, Vijaykrishnan
PY - 2015/1/7
Y1 - 2015/1/7
N2 - Current mode logic (CML) circuits have been widely used in high-speed data transceivers. The lower-voltage-swing makes the switching speed of CML much higher than the static logic can achieve, so it is worthy to adopt the CML circuits at the cost of higher power consumption in the high-speed applications. In order to obtain a better power efficiency (Frequency/power) in CML, it is critical to reduce the power consumption while maintaining the high operating frequency. This paper proposes an alternative approach by building the CML circuits with tunneling-field-effect-transistor (Tunnel FETs or TFETs) to achieve a high-throughput, low-voltage interface circuit design. By taking advantage of its steep subthreshold slope (less than 60 mV/dec), TFET exhibits the same on/off current ratio at the input voltage swing interval much lower than that of the MOSFETs, which enables the supply voltage scaling in CML circuits. For a design target data-rate (20 Gbps for multiplexer and 50 Gbps for buffer), our simulations show that the proposed TFET CML circuits are able to reduce the supply voltage from 0.6 V in conventional Si FinFET CML circuits to as low as 0.3 V while using the same constant tail current. As a result, a power consumption reduction of approximately 50% is achieved by the proposed TFET CML circuits, making the TFET CML approach a promising candidate for future low-power, high-performance applications.
AB - Current mode logic (CML) circuits have been widely used in high-speed data transceivers. The lower-voltage-swing makes the switching speed of CML much higher than the static logic can achieve, so it is worthy to adopt the CML circuits at the cost of higher power consumption in the high-speed applications. In order to obtain a better power efficiency (Frequency/power) in CML, it is critical to reduce the power consumption while maintaining the high operating frequency. This paper proposes an alternative approach by building the CML circuits with tunneling-field-effect-transistor (Tunnel FETs or TFETs) to achieve a high-throughput, low-voltage interface circuit design. By taking advantage of its steep subthreshold slope (less than 60 mV/dec), TFET exhibits the same on/off current ratio at the input voltage swing interval much lower than that of the MOSFETs, which enables the supply voltage scaling in CML circuits. For a design target data-rate (20 Gbps for multiplexer and 50 Gbps for buffer), our simulations show that the proposed TFET CML circuits are able to reduce the supply voltage from 0.6 V in conventional Si FinFET CML circuits to as low as 0.3 V while using the same constant tail current. As a result, a power consumption reduction of approximately 50% is achieved by the proposed TFET CML circuits, making the TFET CML approach a promising candidate for future low-power, high-performance applications.
UR - http://www.scopus.com/inward/record.url?scp=84936865455&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84936865455&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2014.7004179
DO - 10.1109/VLSI-SoC.2014.7004179
M3 - Conference contribution
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
BT - 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings
A2 - Garcia, Lorena
PB - IEEE Computer Society
T2 - 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
Y2 - 6 October 2014 through 8 October 2014
ER -