Making B+ -tree efficient in PCM-based main memory

Ping Chi; Wang Chien Lee; Yuan Xie

doi:10.1145/2627369.2627630

Making B⁺ -tree efficient in PCM-based main memory

Ping Chi
, Wang Chien Lee
, Yuan Xie

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

35 Scopus citations

Abstract

Phase change memory (PCM) is a promising technology for building future large-scale and low-power main memory systems. Main memory databases (MMDBs) can benefit from the high density of PCM. However, its long write latency, high write energy, and limited lifetime, bring challenges to database algorithm design for PCM-based memory systems. In this paper, we focus on making B ⁺-tree PCM-friendly by reducing the write accesses to PCM. We propose three different schemes. Experimental results show that they can efficiently improve the performance, reduce the memory energy consumption, and improve the lifetime for PCM memory.

Original language	English (US)
Title of host publication	ISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-74
Number of pages	6
ISBN (Print)	9781450329750
DOIs	https://doi.org/10.1145/2627369.2627630
State	Published - 2014
Event	2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014 - San Diego, CA, United States Duration: Aug 11 2014 → Aug 13 2014

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014
Country/Territory	United States
City	San Diego, CA
Period	8/11/14 → 8/13/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1145/2627369.2627630

Cite this

Chi, P., Lee, W. C., & Xie, Y. (2014). Making B⁺ -tree efficient in PCM-based main memory. In ISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design (pp. 69-74). (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2627369.2627630

@inproceedings{8682f2ddd99248e487b2a11e2dabdcf3,

title = "Making B+ -tree efficient in PCM-based main memory",

abstract = "Phase change memory (PCM) is a promising technology for building future large-scale and low-power main memory systems. Main memory databases (MMDBs) can benefit from the high density of PCM. However, its long write latency, high write energy, and limited lifetime, bring challenges to database algorithm design for PCM-based memory systems. In this paper, we focus on making B +-tree PCM-friendly by reducing the write accesses to PCM. We propose three different schemes. Experimental results show that they can efficiently improve the performance, reduce the memory energy consumption, and improve the lifetime for PCM memory.",

author = "Ping Chi and Lee, \{Wang Chien\} and Yuan Xie",

note = "Copyright: Copyright 2014 Elsevier B.V., All rights reserved.; 2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014 ; Conference date: 11-08-2014 Through 13-08-2014",

year = "2014",

doi = "10.1145/2627369.2627630",

language = "English (US)",

isbn = "9781450329750",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "69--74",

booktitle = "ISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design",

address = "United States",

}

Chi, P, Lee, WC & Xie, Y 2014, Making B⁺ -tree efficient in PCM-based main memory. in ISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., pp. 69-74, 2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014, San Diego, CA, United States, 8/11/14. https://doi.org/10.1145/2627369.2627630

Making B⁺ -tree efficient in PCM-based main memory. / Chi, Ping; Lee, Wang Chien; Xie, Yuan.
ISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2014. p. 69-74 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Making B+ -tree efficient in PCM-based main memory

AU - Chi, Ping

AU - Lee, Wang Chien

AU - Xie, Yuan

PY - 2014

Y1 - 2014

N2 - Phase change memory (PCM) is a promising technology for building future large-scale and low-power main memory systems. Main memory databases (MMDBs) can benefit from the high density of PCM. However, its long write latency, high write energy, and limited lifetime, bring challenges to database algorithm design for PCM-based memory systems. In this paper, we focus on making B +-tree PCM-friendly by reducing the write accesses to PCM. We propose three different schemes. Experimental results show that they can efficiently improve the performance, reduce the memory energy consumption, and improve the lifetime for PCM memory.

AB - Phase change memory (PCM) is a promising technology for building future large-scale and low-power main memory systems. Main memory databases (MMDBs) can benefit from the high density of PCM. However, its long write latency, high write energy, and limited lifetime, bring challenges to database algorithm design for PCM-based memory systems. In this paper, we focus on making B +-tree PCM-friendly by reducing the write accesses to PCM. We propose three different schemes. Experimental results show that they can efficiently improve the performance, reduce the memory energy consumption, and improve the lifetime for PCM memory.

UR - https://www.scopus.com/pages/publications/84906810742

UR - https://www.scopus.com/pages/publications/84906810742#tab=citedBy

U2 - 10.1145/2627369.2627630

DO - 10.1145/2627369.2627630

M3 - Conference contribution

AN - SCOPUS:84906810742

SN - 9781450329750

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 69

EP - 74

BT - ISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014

Y2 - 11 August 2014 through 13 August 2014

ER -