TY - GEN
T1 - Managing signal and power integrity using power transmission lines and alternative signaling schemes
AU - Telikepalli, Satyanarayana
AU - Kim, Sang Kyu
AU - Park, Sung Joo
AU - Swaminathan, Madhavan
AU - Han, Youkeun
PY - 2013
Y1 - 2013
N2 - Signal and power integrity are crucial for ensuring good performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) becomes a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). Previous works have demonstrated the validity of the Power Transmission Line concept in terms of SSN reduction and power consumption reduction [1-4]. However, these works focused on small systems with just a few bits. This paper shows the effectiveness of the PTL concept on a large scale system with a large number of I/O pins through an FPGA implementation to simulate the memory interface such as DDR3.
AB - Signal and power integrity are crucial for ensuring good performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) becomes a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). Previous works have demonstrated the validity of the Power Transmission Line concept in terms of SSN reduction and power consumption reduction [1-4]. However, these works focused on small systems with just a few bits. This paper shows the effectiveness of the PTL concept on a large scale system with a large number of I/O pins through an FPGA implementation to simulate the memory interface such as DDR3.
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U2 - 10.1109/LASCAS.2013.6519089
DO - 10.1109/LASCAS.2013.6519089
M3 - Conference contribution
AN - SCOPUS:84879387974
SN - 9781424494859
T3 - 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings
BT - 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings
T2 - 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013
Y2 - 27 February 2013 through 1 March 2013
ER -