Manufacturing Challenges of Czochralski Growth and Fabrication of 2-inch Semi-Insulating β-Ga2O3 Substrates

J. Blevins, A. Brady, G. Foundos, C. Scott, D. Snyder, W. Everson, R. Lavelle, V. Gambin

Research output: Contribution to conferencePaperpeer-review

2 Scopus citations

Abstract

In recent years, beta-phase gallium oxide (β-Ga2O3) has emerged as an attractive candidate for next generation high voltage power switching and high frequency transistors. This is primarily due to its ultra-wide bandgap of 4.9 eV and high electric field breakdown of 8 MV/cm as well as being the only wide bandgap semiconductor capable of crystallization from a melt utilizing industrial scale manufacturing techniques such as the Czochralski (CZ) method. CZ crystal growth, fabrication, and polishing of β-Ga2O3 single crystals introduce unique process challenges not encountered with other compound semiconductors. Fabrication of single crystal β-Ga2O3 boules into epi-ready substrates is complicated by the presence of active (100) and (001) cleavage planes which are highly susceptible to mechanical stress and can easily form cracks during boule fabrication processes such as coring, outside diameter and flat grinding, wire sawing, and polishing. In this paper, we will review an Air Force Research Laboratory (AFRL) funded effort with SYNOPTICS and the Penn State University Applied Research Laboratory (PSU/ARL) for development and commercialization of 2-inch semi-insulating (010) β-Ga2O3 substrates with improved crystalline quality and sub-nm surface roughness. In this effort, improvements were made in boule growth and processing into wafers, the depth of damage for wafer processing steps was analyzed and shown to be up to 100 μm, and an improved, high removal rate, multi-step polishing process was developed to eliminate subsurface damage. This process yields in an epi-ready surface with a ~10X reduction in polishing cycle time. Typical x-ray rocking curve measurements for the new process were consistently < 75 arcsec with an average surface roughness of < 3 Å. Additionally, an etching and mapping method was developed to analyze dislocation and nano-pipe distribution and map defect density for 2-inch wafers.

Original languageEnglish (US)
Pages291-294
Number of pages4
StatePublished - 2022
Event2022 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2022 - Monterey, United States
Duration: May 9 2022May 12 2022

Conference

Conference2022 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2022
Country/TerritoryUnited States
CityMonterey
Period5/9/225/12/22

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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