@inproceedings{a18c167e9f9640f09bdfee3100590c33,
title = "Mapping high-dimension wavefront computations to silicon",
abstract = "The authors present a new template-matching algorithm with good recognition performance. However, this new algorithm exhibits a complex, four-dimensional, wavefront architecture. Thus, for VLSI implementation, reduced architectures with fewer connections and processors need to be derived. For this purpose, the authors develop a systematic reduction methodology to manually map wavefront computations from high-dimension to low-dimension. This methodology consists of seven steps. Based on this methodology, the authors derive several two-dimensional architectures which are suitable for VLSI implementation for the new template-matching algorithm and have simulated one of the architectures by using the Intel Hypercube Machine iPSC/2.",
author = "Wu, {Chen Mie} and Owens, {Robert M.} and Irwin, {Mary J.}",
year = "1991",
month = jan,
day = "1",
language = "English (US)",
isbn = "0818690895",
series = "Proc 90 Int Conf Appl Specif Array Process",
publisher = "Publ by IEEE",
pages = "78--89",
booktitle = "Proc 90 Int Conf Appl Specif Array Process",
note = "Proceedings of the 1990 International Conference on Application Specific Array Processors ; Conference date: 05-09-1990 Through 07-09-1990",
}