Memory Systems and Compiler Support for MPSoC Architectures

Mahmut Kandemir, Nikil Dutt

Research output: Chapter in Book/Report/Conference proceedingChapter

15 Scopus citations


This chapter focuses on the optimization of the memory performance of an multiprocessor systems-on-chips MPSoC-based system. Multiprocessor configuration provides an opportunity for energy savings through a careful and selective management of individual processors. An on-chip multiprocessor is a suitable platform for executing array-intensive computations that are commonly found in embedded image and video processing applications. One of the most critical components that determine the success of an MPSoC based architecture is its memory system. Memory system performance is critical to both performance and power consumption. The two major ways of optimizing the memory performance of an MPSoC-based system are-constructing a suitable memory organization/hierarchy and optimizing the software for it. On the architecture side, one can employ a traditional cache-based hierarchy or can opt to build a customized memory hierarchy, which can consist of caches; scratch pad memories; stream buffers; last-in, first-out protocols (LIFOs); or a combination of these. It is also possible to make some architectural features reconfigurable and tune their parameters at run time, according to the needs of the application being executed. The chapter also describes different memory architectures for MPSoCs. It reviews several MPSoC compilation issues including constraint-based compilation, which compiles a given application code for an objective function, and under several constraints based on performance, energy/power, and memory usage.

Original languageEnglish (US)
Title of host publicationMultiprocessor Systems-on-Chips
PublisherElsevier Inc.
Number of pages31
ISBN (Print)9780123852519
StatePublished - 2005

All Science Journal Classification (ASJC) codes

  • General Computer Science


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