TY - GEN
T1 - Methodologies to exploit ATPG tools for de-camouflaging
AU - Vontela, Deepakreddy
AU - Ghosh, Swaroop
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/2
Y1 - 2017/5/2
N2 - Semiconductor supply chain is increasingly getting exposed to Reverse Engineering (RE) of Intellectual Property (IP). Camouflaging of gates are typically employed to hide the gate functionality to prevent RE. Adversaries perform RE by developing custom software to determine test patterns and analyze the outputs. In this paper, we show that RE of camouflaged design can be performed by exploiting the test features of commercial/publicly available Automatic Test Pattern Generation (ATPG) tools. We also propose a controllability/observability and Hamming Distance sensitivity based metric to select target gates for camouflaging. Our simulation shows that the proposed techniques can increase the RE effort significantly by camouflaging small fraction of gates.
AB - Semiconductor supply chain is increasingly getting exposed to Reverse Engineering (RE) of Intellectual Property (IP). Camouflaging of gates are typically employed to hide the gate functionality to prevent RE. Adversaries perform RE by developing custom software to determine test patterns and analyze the outputs. In this paper, we show that RE of camouflaged design can be performed by exploiting the test features of commercial/publicly available Automatic Test Pattern Generation (ATPG) tools. We also propose a controllability/observability and Hamming Distance sensitivity based metric to select target gates for camouflaging. Our simulation shows that the proposed techniques can increase the RE effort significantly by camouflaging small fraction of gates.
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U2 - 10.1109/ISQED.2017.7918324
DO - 10.1109/ISQED.2017.7918324
M3 - Conference contribution
AN - SCOPUS:85019635595
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 250
EP - 256
BT - Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PB - IEEE Computer Society
T2 - 18th International Symposium on Quality Electronic Design, ISQED 2017
Y2 - 14 March 2017 through 15 March 2017
ER -