Mini-computer PDP-8 ISA simulator design and verification

Tarek Elarabi, Ranjith Kumar, Rajath Mavathur Basavaraj

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper introduces a simple instruction set architecture simulator for the PDP-8 mini-computer. It generates a memory trace file from an assembled input object file. The memory trace file indicates whether the access was an instruction fetch, data read or data write. The simulator supports all instructions except for input/output and group 3 microinstructions. A summary of the total number of instructions executed, clock cycles consumed and instruction count by mnemonic is outputted at the end of simulation. A branch trace file is generated listing instruction branches by program counter, branch type, target address and whether taken or not.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 UKSim-AMSS 20th International Conference on Modelling and Simulation, UKSim 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages175-180
Number of pages6
ISBN (Electronic)9781538658789
DOIs
StatePublished - Dec 24 2018
Event20th IEEE UKSim-AMSS International Conference on Modelling and Simulation, UKSim 2018 - Cambridge, Cambridgeshire, United Kingdom
Duration: Mar 27 2018Mar 29 2018

Publication series

NameProceedings - 2018 UKSim-AMSS 20th International Conference on Modelling and Simulation, UKSim 2018

Conference

Conference20th IEEE UKSim-AMSS International Conference on Modelling and Simulation, UKSim 2018
Country/TerritoryUnited Kingdom
CityCambridge, Cambridgeshire
Period3/27/183/29/18

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Science Applications
  • Modeling and Simulation

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