Mixed-signal System-on-a-Chip (SoC) verification based on SystemVerilog model

Xiaokun Yang, Xinwei Niu, Jeffrey Fan, Chiu Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Simulation speed and a lack of test approaches are the main difficulties in the mixed-signal verification of a complex System-on-a-Chip (SoC). In this paper, an equivalent high-level Radio Frequency (RF) model is created by the SystemVerilog language and integrated into a mixed-signal SoC. Such a model can be executed on a digital simulator, which is dramatically faster than the traditional method using an analog solver. Some mixed-signal verification approaches based on digital methods (including constrained random data generation, assertion-based verification, coverage-driven verification, and Verification Methodology Manual) are also presented as well as a case on the integrated SoC.

Original languageEnglish (US)
Title of host publication45th Southeastern Symposium on System Theory, SSST 2013
Pages17-21
Number of pages5
DOIs
StatePublished - 2013
Event45th Southeastern Symposium on System Theory, SSST 2013 - Waco, TX, United States
Duration: Mar 11 2013Mar 11 2013

Publication series

NameProceedings of the Annual Southeastern Symposium on System Theory

Conference

Conference45th Southeastern Symposium on System Theory, SSST 2013
Country/TerritoryUnited States
CityWaco, TX
Period3/11/133/11/13

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • General Mathematics

Fingerprint

Dive into the research topics of 'Mixed-signal System-on-a-Chip (SoC) verification based on SystemVerilog model'. Together they form a unique fingerprint.

Cite this