TY - GEN
T1 - MLC PCM main memory with accelerated read
AU - Arjomand, Mohammad
AU - Jadidi, Amin
AU - Kandemir, Mahmut T.
AU - Sivasubramaniam, Anand
AU - Das, Chita
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/31
Y1 - 2016/5/31
N2 - This paper alleviates the problem of slow reads in the Multi-Level Cell Phase Change Memory (MLC PCM) by exploiting a the fact that the Most-Significant Bit (MSB) of MLCs is read fast, while reading the Least-Significant Bits (LSBs) is slower. We propose Half-Line PCM (HL-PCM), a memory architecture that leverages this property to send half of a cache line to the processor ahead of the other half, so that processor continues its execution if the missed data element is in the first half. Our evaluation shows that HL-PCM improves program execution time by 23%, on average, in a 16-core CMP model for workloads from PARSEC-2 benchmark.
AB - This paper alleviates the problem of slow reads in the Multi-Level Cell Phase Change Memory (MLC PCM) by exploiting a the fact that the Most-Significant Bit (MSB) of MLCs is read fast, while reading the Least-Significant Bits (LSBs) is slower. We propose Half-Line PCM (HL-PCM), a memory architecture that leverages this property to send half of a cache line to the processor ahead of the other half, so that processor continues its execution if the missed data element is in the first half. Our evaluation shows that HL-PCM improves program execution time by 23%, on average, in a 16-core CMP model for workloads from PARSEC-2 benchmark.
UR - http://www.scopus.com/inward/record.url?scp=84978656486&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84978656486&partnerID=8YFLogxK
U2 - 10.1109/ISPASS.2016.7482082
DO - 10.1109/ISPASS.2016.7482082
M3 - Conference contribution
AN - SCOPUS:84978656486
T3 - ISPASS 2016 - International Symposium on Performance Analysis of Systems and Software
SP - 143
EP - 144
BT - ISPASS 2016 - International Symposium on Performance Analysis of Systems and Software
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International Symposium on Performance Analysis of Systems and Software, ISPASS 2016
Y2 - 17 April 2016 through 19 April 2016
ER -