TY - GEN
T1 - Modeling and analysis of domain wall dynamics for robust and low-power embedded memory
AU - Iyengar, Anirudh
AU - Ghosh, Swaroop
PY - 2014
Y1 - 2014
N2 - Non-volatile memories are gaining significant attention for embedded cache application due to low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we provide a physics-based model of domain wall that comprehends process variations (PV) and Joule heating. The proposed model has been used for circuit simulation. We also propose techniques to mitigate the impact of variability and Joule heating while enabling low-power and high frequency operation.
AB - Non-volatile memories are gaining significant attention for embedded cache application due to low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we provide a physics-based model of domain wall that comprehends process variations (PV) and Joule heating. The proposed model has been used for circuit simulation. We also propose techniques to mitigate the impact of variability and Joule heating while enabling low-power and high frequency operation.
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U2 - 10.1145/2593069.2593161
DO - 10.1145/2593069.2593161
M3 - Conference contribution
AN - SCOPUS:84903170714
SN - 9781479930173
T3 - Proceedings - Design Automation Conference
BT - DAC 2014 - 51st Design Automation Conference, Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 51st Annual Design Automation Conference, DAC 2014
Y2 - 2 June 2014 through 5 June 2014
ER -