TY - JOUR
T1 - Modeling and analysis of power distribution networks for gigabit applications
AU - Choi, Jinwoo
AU - Min, Sung Hwan
AU - Kim, Joong Ho
AU - Swaminathan, Madhavan
AU - Beyene, Wendemagegnehu
AU - Yuan, Xingchao
N1 - Funding Information:
This work was supported in part by Semiconductor Research Corporation under Georgia Tech ID E21-F05, by the US National Science Foundation under Georgia Tech ID E21-N33, by the US DARPA Neocad Program under Georgia Tech ID E21-6BE, and by Yamacraw, a state-funded intitiative in the State of Georgia.
PY - 2003/10
Y1 - 2003/10
N2 - As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PBGA) packages on a PCB. In this paper, a hybrid method has been applied for analysis which consists of the Transmission Matrix Method (TMM) in the frequency domain and Macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.
AB - As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PBGA) packages on a PCB. In this paper, a hybrid method has been applied for analysis which consists of the Transmission Matrix Method (TMM) in the frequency domain and Macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.
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U2 - 10.1109/TMC.2003.1255645
DO - 10.1109/TMC.2003.1255645
M3 - Article
AN - SCOPUS:3042767730
SN - 1536-1233
VL - 2
SP - 299
EP - 313
JO - IEEE Transactions on Mobile Computing
JF - IEEE Transactions on Mobile Computing
IS - 4
ER -