Modeling and design of system-in-package integrated voltage regulator with thermal effects

S. Mueller, A. K. Davis, M. L.F. Bellaredj, A. Singh, K. Z. Ahmed, M. Kar, S. Mukhopadhyay, P. A. Kohl, M. Swaminathan, Y. Wang, J. Wong, S. Bharathi, Y. Mano, A. Beece, B. Fasano, H. Fathi Moghadam, D. Draper

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

This paper demonstrates a new approach to model the impact of thermal effects on the efficiency of integrated voltage regulators (IVRs) by combining analytical efficiency evaluations with coupled electrical and thermal simulations. An application of the approach shows that a system-in-package solution avoids thermal problems typically observed in other IVR designs. While the evaluation in this paper focuses on the thermal impact on loss in the inductor wiring and the PDN, the developed approach is general enough to also model thermal impacts on the power dissipation in the inductor cores and the buck converter chip.

Original languageEnglish (US)
Title of host publication2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages65-67
Number of pages3
ISBN (Electronic)9781509022724
DOIs
StatePublished - Jan 26 2017
Event25th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2016 - San Diego, United States
Duration: Oct 23 2016Oct 26 2016

Publication series

Name2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2016

Conference

Conference25th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2016
Country/TerritoryUnited States
CitySan Diego
Period10/23/1610/26/16

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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