Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs

Kai Fu; Wen Sheng Zhao; Gaofeng Wang; Madhavan Swaminathan

doi:10.1109/ACCESS.2018.2846751

Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs

Kai Fu
, Wen Sheng Zhao
, Gaofeng Wang
, Madhavan Swaminathan

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

14 Scopus citations

Abstract

A shielded-differential annular through-silicon via (SD-ATSV) is proposed and investigated. The equivalent circuit model is developed with the influence of the electrically floating silicon substrate taken into account. By virtue of the circuit model, the frequency-and time-domain electrical characterizations of the SD-ATSV are conducted. Furthermore, the thermo-mechanical stress of the SD-ATSV is captured and compared with that of the shielded-differential cylindrical through-silicon via. It is demonstrated that by utilizing the SD-ATSV, the keep-out zone can be reduced without performance degradation.

Original language	English (US)
Pages (from-to)	33238-33250
Number of pages	13
Journal	IEEE Access
Volume	6
DOIs	https://doi.org/10.1109/ACCESS.2018.2846751
State	Published - Jun 12 2018

All Science Journal Classification (ASJC) codes

General Computer Science
General Materials Science
General Engineering

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@article{10d1eb5169c445f083a0ed3e7ccbb4e6,

title = "Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs",

abstract = "A shielded-differential annular through-silicon via (SD-ATSV) is proposed and investigated. The equivalent circuit model is developed with the influence of the electrically floating silicon substrate taken into account. By virtue of the circuit model, the frequency-and time-domain electrical characterizations of the SD-ATSV are conducted. Furthermore, the thermo-mechanical stress of the SD-ATSV is captured and compared with that of the shielded-differential cylindrical through-silicon via. It is demonstrated that by utilizing the SD-ATSV, the keep-out zone can be reduced without performance degradation.",

author = "Kai Fu and Zhao, \{Wen Sheng\} and Gaofeng Wang and Madhavan Swaminathan",

note = "Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2018",

month = jun,

day = "12",

doi = "10.1109/ACCESS.2018.2846751",

language = "English (US)",

volume = "6",

pages = "33238--33250",

journal = "IEEE Access",

issn = "2169-3536",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs

AU - Fu, Kai

AU - Zhao, Wen Sheng

AU - Wang, Gaofeng

AU - Swaminathan, Madhavan

PY - 2018/6/12

Y1 - 2018/6/12

N2 - A shielded-differential annular through-silicon via (SD-ATSV) is proposed and investigated. The equivalent circuit model is developed with the influence of the electrically floating silicon substrate taken into account. By virtue of the circuit model, the frequency-and time-domain electrical characterizations of the SD-ATSV are conducted. Furthermore, the thermo-mechanical stress of the SD-ATSV is captured and compared with that of the shielded-differential cylindrical through-silicon via. It is demonstrated that by utilizing the SD-ATSV, the keep-out zone can be reduced without performance degradation.

AB - A shielded-differential annular through-silicon via (SD-ATSV) is proposed and investigated. The equivalent circuit model is developed with the influence of the electrically floating silicon substrate taken into account. By virtue of the circuit model, the frequency-and time-domain electrical characterizations of the SD-ATSV are conducted. Furthermore, the thermo-mechanical stress of the SD-ATSV is captured and compared with that of the shielded-differential cylindrical through-silicon via. It is demonstrated that by utilizing the SD-ATSV, the keep-out zone can be reduced without performance degradation.

UR - https://www.scopus.com/pages/publications/85048522578

UR - https://www.scopus.com/pages/publications/85048522578#tab=citedBy

U2 - 10.1109/ACCESS.2018.2846751

DO - 10.1109/ACCESS.2018.2846751

M3 - Article

AN - SCOPUS:85048522578

SN - 2169-3536

VL - 6

SP - 33238

EP - 33250

JO - IEEE Access

JF - IEEE Access

ER -

Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs

Abstract

All Science Journal Classification (ASJC) codes

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