Modeling and simulation of core switching noise for ASICs

Nju Na, Jinwoo Choi, Madhavan Swaminathan, James P. Libous, Daniel P. O'Connor

Research output: Contribution to journalArticlepeer-review

23 Scopus citations


This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resOnances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.

Original languageEnglish (US)
Pages (from-to)4-11
Number of pages8
JournalIEEE Transactions on Advanced Packaging
Issue number1
StatePublished - Feb 2002

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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