Modeling energy of the clock generation and distribution circuitry

David Duarte, Mary Jane Irwin, Vijaykrishnan Narayanan

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations


In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9% as compared to the actual values.

Original languageEnglish (US)
Pages (from-to)261-265
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - 2000
EventProceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Duration: Sep 13 2000Sep 16 2000

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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