Modeling energy of the clock generation and distribution circuitry

David Duarte; Mary Jane Irwin; Vijaykrishnan Narayanan

Modeling energy of the clock generation and distribution circuitry

David Duarte
, Mary Jane Irwin
, Vijaykrishnan Narayanan

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9% as compared to the actual values.

Original language	English (US)
Pages (from-to)	261-265
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - 2000
Event	Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: Sep 13 2000 → Sep 16 2000

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "Modeling energy of the clock generation and distribution circuitry",

abstract = "In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9\% as compared to the actual values.",

author = "David Duarte and Irwin, \{Mary Jane\} and Vijaykrishnan Narayanan",

year = "2000",

language = "English (US)",

pages = "261--265",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 13th Annual IEEE International ASIC/SOC Conference ; Conference date: 13-09-2000 Through 16-09-2000",

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T1 - Modeling energy of the clock generation and distribution circuitry

AU - Duarte, David

AU - Irwin, Mary Jane

AU - Narayanan, Vijaykrishnan

PY - 2000

Y1 - 2000

N2 - In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9% as compared to the actual values.

AB - In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9% as compared to the actual values.

UR - https://www.scopus.com/pages/publications/0033681845

UR - https://www.scopus.com/pages/publications/0033681845#tab=citedBy

M3 - Conference article

AN - SCOPUS:0033681845

SN - 1063-0988

SP - 261

EP - 265

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 13th Annual IEEE International ASIC/SOC Conference

Y2 - 13 September 2000 through 16 September 2000

ER -

Modeling energy of the clock generation and distribution circuitry

Abstract

All Science Journal Classification (ASJC) codes

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