TY - GEN
T1 - Modeling of multi-layered power distribution planes including via effects using transmission matrix method
AU - Kim, Joong Ho
AU - Matoglu, E.
AU - Choi, Jinwoo
AU - Swaminathan, M.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - This paper presents a method for analyzing multilayered power distribution networks in the frequency domain. Using a two dimensional array of distributed RLCG circuits, multi-layered power distribution planes are represented. Each plane pair is connected by vias, which are modeled as partial self and mutual inductors. For the efficient computation of the power distribution impedances at specific points in the network, a multiinput and multi-output transmission matrix method has been used, which is much faster than Spice and reduces memory requirements. This method has been compared with the cavity resonator method simulated in Spice.
AB - This paper presents a method for analyzing multilayered power distribution networks in the frequency domain. Using a two dimensional array of distributed RLCG circuits, multi-layered power distribution planes are represented. Each plane pair is connected by vias, which are modeled as partial self and mutual inductors. For the efficient computation of the power distribution impedances at specific points in the network, a multiinput and multi-output transmission matrix method has been used, which is much faster than Spice and reduces memory requirements. This method has been compared with the cavity resonator method simulated in Spice.
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U2 - 10.1109/ASPDAC.2002.994886
DO - 10.1109/ASPDAC.2002.994886
M3 - Conference contribution
AN - SCOPUS:84962326735
T3 - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
SP - 59
EP - 64
BT - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Y2 - 7 January 2002 through 11 January 2002
ER -