TY - GEN
T1 - Modeling of Power Distribution Networks for path finding
AU - Han, Ki Jin
AU - Sandeep, Srikumar
AU - Martin, Bill
AU - Swaminathan, Madhavan
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/12/3
Y1 - 2015/12/3
N2 - In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.
AB - In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.
UR - http://www.scopus.com/inward/record.url?scp=84962852769&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962852769&partnerID=8YFLogxK
U2 - 10.1109/EPEPS.2015.7347119
DO - 10.1109/EPEPS.2015.7347119
M3 - Conference contribution
AN - SCOPUS:84962852769
T3 - 2015 IEEE 24th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
SP - 11
EP - 14
BT - 2015 IEEE 24th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
Y2 - 25 October 2015 through 28 October 2015
ER -