Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method

Jinseong Choi, Madhavan Swaminathan, Nhon Do, Raj Master

Research output: Contribution to journalArticlepeer-review

35 Scopus citations

Abstract

In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately.

Original languageEnglish (US)
Pages (from-to)424-439
Number of pages16
JournalIEEE Transactions on Electromagnetic Compatibility
Volume47
Issue number3
DOIs
StatePublished - Aug 2005

All Science Journal Classification (ASJC) codes

  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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