Modeling of power supply noise in large chips with nonlinear circuits

Jinseong Choi, Madhavan Swaminathan, Nhon Do, Raj Master

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.

Original languageEnglish (US)
Title of host publicationElectrical Performance of Electronic Packaging, EPEP 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages257-260
Number of pages4
ISBN (Electronic)0780374517
DOIs
StatePublished - 2002
Event11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 - Monterey, United States
Duration: Oct 21 2002Oct 23 2002

Publication series

NameIEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume2002-January

Conference

Conference11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Country/TerritoryUnited States
CityMonterey
Period10/21/0210/23/02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

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