Modeling of power supply noise in large chips with nonlinear circuits

Jinseong Choi; Madhavan Swaminathan; Nhon Do; Raj Master

doi:10.1109/EPEP.2002.1057927

Modeling of power supply noise in large chips with nonlinear circuits

Jinseong Choi, Madhavan Swaminathan, Nhon Do, Raj Master

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.

Original language	English (US)
Title of host publication	Electrical Performance of Electronic Packaging, EPEP 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	257-260
Number of pages	4
ISBN (Electronic)	0780374517
DOIs	https://doi.org/10.1109/EPEP.2002.1057927
State	Published - 2002
Event	11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 - Monterey, United States Duration: Oct 21 2002 → Oct 23 2002

Publication series

Name	IEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume	2002-January

Conference

Conference	11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Country/Territory	United States
City	Monterey
Period	10/21/02 → 10/23/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EPEP.2002.1057927

Cite this

Choi, J., Swaminathan, M., Do, N., & Master, R. (2002). Modeling of power supply noise in large chips with nonlinear circuits. In Electrical Performance of Electronic Packaging, EPEP 2002 (pp. 257-260). Article 1057927 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEP.2002.1057927

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title = "Modeling of power supply noise in large chips with nonlinear circuits",

abstract = "In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.",

author = "Jinseong Choi and Madhavan Swaminathan and Nhon Do and Raj Master",

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year = "2002",

doi = "10.1109/EPEP.2002.1057927",

language = "English (US)",

series = "IEEE Topical Meeting on Electrical Performance of Electronic Packaging",

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Choi, J, Swaminathan, M, Do, N & Master, R 2002, Modeling of power supply noise in large chips with nonlinear circuits. in Electrical Performance of Electronic Packaging, EPEP 2002., 1057927, IEEE Topical Meeting on Electrical Performance of Electronic Packaging, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 257-260, 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002, Monterey, United States, 10/21/02. https://doi.org/10.1109/EPEP.2002.1057927

Modeling of power supply noise in large chips with nonlinear circuits. / Choi, Jinseong; Swaminathan, Madhavan; Do, Nhon et al.
Electrical Performance of Electronic Packaging, EPEP 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 257-260 1057927 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Modeling of power supply noise in large chips with nonlinear circuits

AU - Choi, Jinseong

AU - Swaminathan, Madhavan

AU - Do, Nhon

AU - Master, Raj

PY - 2002

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N2 - In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.

AB - In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.

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BT - Electrical Performance of Electronic Packaging, EPEP 2002

PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

Modeling of power supply noise in large chips with nonlinear circuits

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