TY - GEN
T1 - Modeling of power supply noise in large chips with nonlinear circuits
AU - Choi, Jinseong
AU - Swaminathan, Madhavan
AU - Do, Nhon
AU - Master, Raj
N1 - Publisher Copyright:
© 2012 IEEE.
PY - 2002
Y1 - 2002
N2 - In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.
AB - In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit non-linearity on power supply noise.
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U2 - 10.1109/EPEP.2002.1057927
DO - 10.1109/EPEP.2002.1057927
M3 - Conference contribution
AN - SCOPUS:15944411579
T3 - IEEE Topical Meeting on Electrical Performance of Electronic Packaging
SP - 257
EP - 260
BT - Electrical Performance of Electronic Packaging, EPEP 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Y2 - 21 October 2002 through 23 October 2002
ER -