TY - GEN
T1 - Monolithic 3D Integration of 2D Devices
AU - Das, Saptarshi
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Monolithic three-dimensional (3D) integration of 2D materials represents a major breakthrough in semiconductor technology, offering higher device density and multifunctionality [1]. Recently, we achieved large-scale, wafer-level 3D integration of MoS2 and WSe2 field-effect transistors (FETs) across multiple tiers [2]. This work includes 2-tier integration of MoS2 FETs with over 10,000 devices per tier and 3-tier integration of both n-type MoS2 and p-type WSe2 FETs, with approximately 500 devices per tier (Fig. 1). The 3-tier architecture combines multifunctional capabilities, such as logic, memory storage, and sensing, into a single chip. Aggressively scaled MoS2 FETs with channel lengths as short as 45 nm further demonstrate the scalability of this approach. The entire integration process is BEOL-compatible, using low-temperature techniques to prevent degradation of lower-tier devices, marking a significant step toward highly dense, multifunctional 3D integrated circuits based on 2D materials.
AB - Monolithic three-dimensional (3D) integration of 2D materials represents a major breakthrough in semiconductor technology, offering higher device density and multifunctionality [1]. Recently, we achieved large-scale, wafer-level 3D integration of MoS2 and WSe2 field-effect transistors (FETs) across multiple tiers [2]. This work includes 2-tier integration of MoS2 FETs with over 10,000 devices per tier and 3-tier integration of both n-type MoS2 and p-type WSe2 FETs, with approximately 500 devices per tier (Fig. 1). The 3-tier architecture combines multifunctional capabilities, such as logic, memory storage, and sensing, into a single chip. Aggressively scaled MoS2 FETs with channel lengths as short as 45 nm further demonstrate the scalability of this approach. The entire integration process is BEOL-compatible, using low-temperature techniques to prevent degradation of lower-tier devices, marking a significant step toward highly dense, multifunctional 3D integrated circuits based on 2D materials.
UR - https://www.scopus.com/pages/publications/105010835186
UR - https://www.scopus.com/inward/citedby.url?scp=105010835186&partnerID=8YFLogxK
U2 - 10.1109/EDTM61175.2025.11040484
DO - 10.1109/EDTM61175.2025.11040484
M3 - Conference contribution
AN - SCOPUS:105010835186
T3 - 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025
BT - 9th IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2025
Y2 - 9 March 2025 through 12 March 2025
ER -