Monolithic 3D+-IC based Reconfigurable Compute-in-Memory SRAM Macro

Srivatsa Srinivasa; Yung Ning Tu; Xin Si; Cheng Xin Xue; Chun Ying Lee; Fu Kuo Hsueh; Chane Hone Shen; Jia Min Shieh; Wen Kuan Yeh; Akshay Krishna Ramanathan; Mon Shu Ho; Jack Sampson; Meng Fan Chang; Vijaykrishnan Narayanan

doi:10.23919/VLSIT.2019.8776506

Monolithic 3D⁺-IC based Reconfigurable Compute-in-Memory SRAM Macro

Srivatsa Srinivasa, Yung Ning Tu, Xin Si, Cheng Xin Xue, Chun Ying Lee, Fu Kuo Hsueh, Chane Hone Shen, Jia Min Shieh, Wen Kuan Yeh, Akshay Krishna Ramanathan, Mon Shu Ho, Jack Sampson, Meng Fan Chang, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D⁺-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V V_ddmin 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.

Original language	English (US)
Title of host publication	2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T32-T33
ISBN (Electronic)	9784863487178
DOIs	https://doi.org/10.23919/VLSIT.2019.8776506
State	Published - Jun 2019
Event	39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan Duration: Jun 9 2019 → Jun 14 2019

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2019-June
ISSN (Print)	0743-1562

Conference

Conference	39th Symposium on VLSI Technology, VLSI Technology 2019
Country/Territory	Japan
City	Kyoto
Period	6/9/19 → 6/14/19

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.23919/VLSIT.2019.8776506

Cite this

Srinivasa, S., Tu, Y. N., Si, X., Xue, C. X., Lee, C. Y., Hsueh, F. K., Shen, C. H., Shieh, J. M., Yeh, W. K., Ramanathan, A. K., Ho, M. S., Sampson, J., Chang, M. F., & Narayanan, V. (2019). Monolithic 3D⁺-IC based Reconfigurable Compute-in-Memory SRAM Macro. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T32-T33). Article 8776506 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776506

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title = "Monolithic 3D+-IC based Reconfigurable Compute-in-Memory SRAM Macro",

abstract = "This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V Vddmin 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.",

author = "Srivatsa Srinivasa and Tu, {Yung Ning} and Xin Si and Xue, {Cheng Xin} and Lee, {Chun Ying} and Hsueh, {Fu Kuo} and Shen, {Chane Hone} and Shieh, {Jia Min} and Yeh, {Wen Kuan} and Ramanathan, {Akshay Krishna} and Ho, {Mon Shu} and Jack Sampson and Chang, {Meng Fan} and Vijaykrishnan Narayanan",

note = "Publisher Copyright: {\textcopyright} 2019 The Japan Society of Applied Physics.; 39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

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Srinivasa, S, Tu, YN, Si, X, Xue, CX, Lee, CY, Hsueh, FK, Shen, CH, Shieh, JM, Yeh, WK, Ramanathan, AK, Ho, MS, Sampson, J, Chang, MF & Narayanan, V 2019, Monolithic 3D⁺-IC based Reconfigurable Compute-in-Memory SRAM Macro. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776506, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T32-T33, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 6/9/19. https://doi.org/10.23919/VLSIT.2019.8776506

Monolithic 3D⁺-IC based Reconfigurable Compute-in-Memory SRAM Macro. / Srinivasa, Srivatsa; Tu, Yung Ning; Si, Xin et al.
2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. T32-T33 8776506 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Srinivasa S, Tu YN, Si X, Xue CX, Lee CY, Hsueh FK et al. Monolithic 3D⁺-IC based Reconfigurable Compute-in-Memory SRAM Macro. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. T32-T33. 8776506. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2019.8776506