TY - GEN
T1 - Multi-Bit Read and Write Methodologies for Diode-MTJ Crossbar Array
AU - Khan, Mohammad Nasim Imtiaz
AU - Ghosh, Swaroop
N1 - Funding Information:
This work is supported by the NSF under Award No. CNS –
Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - Crossbar arrays using emerging Non-Volatile Memory (NVM) technologies offer high density, fast access speed and low-power. However, the bandwidth of the crossbar is limited to single-bit read/write per access to avoid the selection of undesirable bits. In this work, we propose a technique to perform multi-bit read and write in a diode-MTJ (Magnetic Tunnel Junction) crossbar array. The simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read which in turn, reduces the sneak path through the half-selected cells. Results indicate biasing the half-selected cells by 700mV can enable reading as much as 512bits while sustaining 512×512 crossbar with 2.04 years retention. During write operation, the half-selected cells are biased with a pulse voltage source in addition to V/2 scheme which increases the write latency of these cells and enables writing 2 bits while keeping the half-selected bits undisturbed. The 2bit writing requires pulsing by 50mV to optimize energy.
AB - Crossbar arrays using emerging Non-Volatile Memory (NVM) technologies offer high density, fast access speed and low-power. However, the bandwidth of the crossbar is limited to single-bit read/write per access to avoid the selection of undesirable bits. In this work, we propose a technique to perform multi-bit read and write in a diode-MTJ (Magnetic Tunnel Junction) crossbar array. The simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read which in turn, reduces the sneak path through the half-selected cells. Results indicate biasing the half-selected cells by 700mV can enable reading as much as 512bits while sustaining 512×512 crossbar with 2.04 years retention. During write operation, the half-selected cells are biased with a pulse voltage source in addition to V/2 scheme which increases the write latency of these cells and enables writing 2 bits while keeping the half-selected bits undisturbed. The 2bit writing requires pulsing by 50mV to optimize energy.
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U2 - 10.1109/ISQED48828.2020.9137015
DO - 10.1109/ISQED48828.2020.9137015
M3 - Conference contribution
AN - SCOPUS:85089957011
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 93
EP - 98
BT - Proceedings of the 21st International Symposium on Quality Electronic Design, ISQED 2020
PB - IEEE Computer Society
T2 - 21st International Symposium on Quality Electronic Design, ISQED 2020
Y2 - 25 March 2020 through 26 March 2020
ER -