Multiple access caches: Energy implications

H. S. Kim, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations


In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Workshop on VLSI 2000
Subtitle of host publicationSystem Design for a System-on-Chip Era, IWV 2000
EditorsHugo De Man, Asim Smailagic, Robert Brodersen
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)0769505341, 9780769505343
StatePublished - 2000
EventIEEE Computer Society Workshop on VLSI, IWV 2000 - Orlando, United States
Duration: Apr 27 2000Apr 28 2000

Publication series

NameProceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000


OtherIEEE Computer Society Workshop on VLSI, IWV 2000
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • General Computer Science


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