Multiple access caches: Energy implications

H. S. Kim; Vijaykrishnan Narayanan; Mahmut Kandemir; Mary Jane Irwin

doi:10.1109/IWV.2000.844530

Multiple access caches: Energy implications

H. S. Kim, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Workshop on VLSI 2000
Subtitle of host publication	System Design for a System-on-Chip Era, IWV 2000
Editors	Hugo De Man, Asim Smailagic, Robert Brodersen
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	53-58
Number of pages	6
ISBN (Electronic)	0769505341, 9780769505343
DOIs	https://doi.org/10.1109/IWV.2000.844530
State	Published - 2000
Event	IEEE Computer Society Workshop on VLSI, IWV 2000 - Orlando, United States Duration: Apr 27 2000 → Apr 28 2000

Publication series

Name	Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000

Other

Other	IEEE Computer Society Workshop on VLSI, IWV 2000
Country/Territory	United States
City	Orlando
Period	4/27/00 → 4/28/00

All Science Journal Classification (ASJC) codes

General Computer Science

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/IWV.2000.844530

Cite this

Kim, H. S., Narayanan, V., Kandemir, M., & Irwin, M. J. (2000). Multiple access caches: Energy implications. In H. De Man, A. Smailagic, & R. Brodersen (Eds.), Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000 (pp. 53-58). Article 844530 (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWV.2000.844530

Kim, H. S. ; Narayanan, Vijaykrishnan ; Kandemir, Mahmut et al. / Multiple access caches : Energy implications. Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000. editor / Hugo De Man ; Asim Smailagic ; Robert Brodersen. Institute of Electrical and Electronics Engineers Inc., 2000. pp. 53-58 (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000).

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title = "Multiple access caches: Energy implications",

abstract = "In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.",

author = "Kim, {H. S.} and Vijaykrishnan Narayanan and Mahmut Kandemir and Irwin, {Mary Jane}",

note = "Publisher Copyright: {\textcopyright} 2000 IEEE.; IEEE Computer Society Workshop on VLSI, IWV 2000 ; Conference date: 27-04-2000 Through 28-04-2000",

year = "2000",

doi = "10.1109/IWV.2000.844530",

language = "English (US)",

series = "Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Kim, HS, Narayanan, V , Kandemir, M & Irwin, MJ 2000, Multiple access caches: Energy implications. in H De Man, A Smailagic & R Brodersen (eds), Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000., 844530, Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000, Institute of Electrical and Electronics Engineers Inc., pp. 53-58, IEEE Computer Society Workshop on VLSI, IWV 2000, Orlando, United States, 4/27/00. https://doi.org/10.1109/IWV.2000.844530

Multiple access caches: Energy implications. / Kim, H. S.; Narayanan, Vijaykrishnan ; Kandemir, Mahmut et al.
Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000. ed. / Hugo De Man; Asim Smailagic; Robert Brodersen. Institute of Electrical and Electronics Engineers Inc., 2000. p. 53-58 844530 (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Multiple access caches

T2 - IEEE Computer Society Workshop on VLSI, IWV 2000

AU - Kim, H. S.

AU - Narayanan, Vijaykrishnan

AU - Kandemir, Mahmut

AU - Irwin, Mary Jane

PY - 2000

Y1 - 2000

N2 - In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.

AB - In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.

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SP - 53

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BT - Proceedings - IEEE Computer Society Workshop on VLSI 2000

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Kim HS, Narayanan V , Kandemir M, Irwin MJ. Multiple access caches: Energy implications. In De Man H, Smailagic A, Brodersen R, editors, Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000. Institute of Electrical and Electronics Engineers Inc. 2000. p. 53-58. 844530. (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000). doi: 10.1109/IWV.2000.844530

Multiple access caches: Energy implications

Abstract

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All Science Journal Classification (ASJC) codes

UN SDGs

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