MULTIPLIER ARCHITECTURE FOR DIGITAL FILTERS.

S. C. Bass; B. J. Leon; W. K. Jenkins

doi:10.1109/cdc.1974.270415

MULTIPLIER ARCHITECTURE FOR DIGITAL FILTERS.

S. C. Bass, B. J. Leon, W. K. Jenkins

Research output: Contribution to conference › Paper › peer-review

Abstract

Since multipliers are the slowest and most expensive components in digital filters, schemes for increasing speed and reducing cost are of interest. For a device that does multiplication by successive shift and add operations, different architectures can be used to speed the process and allow for hardware sharing. Several architectures are discussed in this paper. For filters that carry a small digital word length, nonconventional multiply schemes may well be appropriate. Two such schemes, table look up and residue algebra, are discussed.

Original language	English (US)
Pages	116-121
Number of pages	6
DOIs	https://doi.org/10.1109/cdc.1974.270415
State	Published - 1974
Event	IEEE Conf on Decis and Control, 1974, incl Symp on Adapt Processes, 13th, Proc, Nov 20-22 1974 - Phoenix, AZ, USA Duration: Nov 20 1974 → Nov 22 1974

Other

Other	IEEE Conf on Decis and Control, 1974, incl Symp on Adapt Processes, 13th, Proc, Nov 20-22 1974
City	Phoenix, AZ, USA
Period	11/20/74 → 11/22/74

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/cdc.1974.270415

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title = "MULTIPLIER ARCHITECTURE FOR DIGITAL FILTERS.",

abstract = "Since multipliers are the slowest and most expensive components in digital filters, schemes for increasing speed and reducing cost are of interest. For a device that does multiplication by successive shift and add operations, different architectures can be used to speed the process and allow for hardware sharing. Several architectures are discussed in this paper. For filters that carry a small digital word length, nonconventional multiply schemes may well be appropriate. Two such schemes, table look up and residue algebra, are discussed.",

author = "Bass, {S. C.} and Leon, {B. J.} and Jenkins, {W. K.}",

year = "1974",

doi = "10.1109/cdc.1974.270415",

language = "English (US)",

pages = "116--121",

note = "IEEE Conf on Decis and Control, 1974, incl Symp on Adapt Processes, 13th, Proc, Nov 20-22 1974 ; Conference date: 20-11-1974 Through 22-11-1974",

}

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T1 - MULTIPLIER ARCHITECTURE FOR DIGITAL FILTERS.

AU - Bass, S. C.

AU - Leon, B. J.

AU - Jenkins, W. K.

PY - 1974

Y1 - 1974

N2 - Since multipliers are the slowest and most expensive components in digital filters, schemes for increasing speed and reducing cost are of interest. For a device that does multiplication by successive shift and add operations, different architectures can be used to speed the process and allow for hardware sharing. Several architectures are discussed in this paper. For filters that carry a small digital word length, nonconventional multiply schemes may well be appropriate. Two such schemes, table look up and residue algebra, are discussed.

AB - Since multipliers are the slowest and most expensive components in digital filters, schemes for increasing speed and reducing cost are of interest. For a device that does multiplication by successive shift and add operations, different architectures can be used to speed the process and allow for hardware sharing. Several architectures are discussed in this paper. For filters that carry a small digital word length, nonconventional multiply schemes may well be appropriate. Two such schemes, table look up and residue algebra, are discussed.

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T2 - IEEE Conf on Decis and Control, 1974, incl Symp on Adapt Processes, 13th, Proc, Nov 20-22 1974

Y2 - 20 November 1974 through 22 November 1974

ER -

MULTIPLIER ARCHITECTURE FOR DIGITAL FILTERS.

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