Abstract
Multiresolution Gabor filters are used for feature extraction for a variety of applications. Most hardware implementations have focused on iterative mechanisms on fixed hardware for implementing the different levels of resolution. In contrast, we present a configurable architecture that enhances the resource utilization of the hardware fabric. Our results show that our implementation achieves real-time performance on 2048×1536 images and exhibits 6 times speed up over a GPU implementation. Further, our FPGA implementation achieves an energy-efficiency of processing 0.4 fps/W as compared to the GPU that achieves 0.036 fps/W.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 |
| Pages | 55-60 |
| Number of pages | 6 |
| DOIs | |
| State | Published - 2012 |
| Event | 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Canada Duration: Oct 17 2012 → Oct 19 2012 |
Publication series
| Name | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
|---|---|
| ISSN (Print) | 1520-6130 |
Other
| Other | 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 |
|---|---|
| Country/Territory | Canada |
| City | Quebec City, QC |
| Period | 10/17/12 → 10/19/12 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture
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