Abstract
It is recently demonstrated that gate-definition reactive ion etching of polycrystalline silicon (poly-Si) gate, 0.5 μm channel length MOSFET transistors can cause plasma exposure edge damage in addition to the well-known plasma charging current damage. Here this paper focuses more closely on this gate edge damage and shows for the first time, that it manifests itself as distinct trapping and detrapping localized states at or near the SiO2/substrate Si interface in the thin gate oxide around the gate perimeter.
Original language | English (US) |
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Pages | 84-86 |
Number of pages | 3 |
State | Published - 1996 |
Event | Proceedings of the 1996 1st International Symposium on Plasma Process-Induced Damage, P2ID - Santa Clara, CA, USA Duration: May 13 1996 → May 14 1996 |
Other
Other | Proceedings of the 1996 1st International Symposium on Plasma Process-Induced Damage, P2ID |
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City | Santa Clara, CA, USA |
Period | 5/13/96 → 5/14/96 |
All Science Journal Classification (ASJC) codes
- General Engineering