Noise computation in single chip packages

Kumaresh Bathey; Madhavan Swaminathan; L. D. Smith; T. J. Cockerill

doi:10.1109/96.496039

Noise computation in single chip packages

Kumaresh Bathey, Madhavan Swaminathan, L. D. Smith, T. J. Cockerill

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

20 Scopus citations

Abstract

This paper describes the computation of noise in single chip packages forming an integral part of a larger system. An analysis tool is discussed that integrates the details of chip, first level, and second level packages to form a network for simulation. The tool is useful in the computation of noise generated by single chip packages and allows for post-layout, pre-fabrication noise estimation. This paper provides details on the components of noise including resonance which is often over looked in most computations. Time domain measurements have been used to validate the noise analysis.

Original language	English (US)
Pages (from-to)	350-359
Number of pages	10
Journal	IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging
Volume	19
Issue number	2
DOIs	https://doi.org/10.1109/96.496039
State	Published - May 1996

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/96.496039

Cite this

@article{795330b1608444f59fd45ce6883157f2,

title = "Noise computation in single chip packages",

abstract = "This paper describes the computation of noise in single chip packages forming an integral part of a larger system. An analysis tool is discussed that integrates the details of chip, first level, and second level packages to form a network for simulation. The tool is useful in the computation of noise generated by single chip packages and allows for post-layout, pre-fabrication noise estimation. This paper provides details on the components of noise including resonance which is often over looked in most computations. Time domain measurements have been used to validate the noise analysis.",

author = "Kumaresh Bathey and Madhavan Swaminathan and Smith, {L. D.} and Cockerill, {T. J.}",

note = "Funding Information: Manuscript revised January 1996. This work was supported in part by the Packaging Research Center, Georgia Institute of Technology under National Science Foundation Contract EEC-9402723, K. Bathey and M. Swaminathan are with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA. L. D. Smith is with IBM Corporation, San Jose, CA USA. T. J. Cockerill is with IBM Corporation, Burlington, VT USA. Publisher Item Identifier S 1070-9894(96)03691-2.",

year = "1996",

month = may,

doi = "10.1109/96.496039",

language = "English (US)",

volume = "19",

pages = "350--359",

journal = "IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging",

issn = "1070-9894",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Noise computation in single chip packages

AU - Bathey, Kumaresh

AU - Swaminathan, Madhavan

AU - Smith, L. D.

AU - Cockerill, T. J.

N1 - Funding Information: Manuscript revised January 1996. This work was supported in part by the Packaging Research Center, Georgia Institute of Technology under National Science Foundation Contract EEC-9402723, K. Bathey and M. Swaminathan are with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA. L. D. Smith is with IBM Corporation, San Jose, CA USA. T. J. Cockerill is with IBM Corporation, Burlington, VT USA. Publisher Item Identifier S 1070-9894(96)03691-2.

PY - 1996/5

Y1 - 1996/5

N2 - This paper describes the computation of noise in single chip packages forming an integral part of a larger system. An analysis tool is discussed that integrates the details of chip, first level, and second level packages to form a network for simulation. The tool is useful in the computation of noise generated by single chip packages and allows for post-layout, pre-fabrication noise estimation. This paper provides details on the components of noise including resonance which is often over looked in most computations. Time domain measurements have been used to validate the noise analysis.

AB - This paper describes the computation of noise in single chip packages forming an integral part of a larger system. An analysis tool is discussed that integrates the details of chip, first level, and second level packages to form a network for simulation. The tool is useful in the computation of noise generated by single chip packages and allows for post-layout, pre-fabrication noise estimation. This paper provides details on the components of noise including resonance which is often over looked in most computations. Time domain measurements have been used to validate the noise analysis.

UR - http://www.scopus.com/inward/record.url?scp=0030145293&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030145293&partnerID=8YFLogxK

U2 - 10.1109/96.496039

DO - 10.1109/96.496039

M3 - Article

AN - SCOPUS:0030145293

SN - 1070-9894

VL - 19

SP - 350

EP - 359

JO - IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging

JF - IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging

IS - 2

ER -

Noise computation in single chip packages

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this