TY - GEN
T1 - Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
AU - Thirumala, Sandeep Krishna
AU - Raha, Arnab
AU - Narayanan, Vijaykrishnan
AU - Raghunathan, Vijay
AU - Gupta, Sumeet Kumar
N1 - Funding Information:
ACKNOWLEDGEMENT This work was supported in part by DARPA (#D16AP00109), in part by NSF (#1160483) and in part by SRC (#2016-SD-2723). REFERENCES [1] J. S. Meena, et al., “Overview of Emerging Nonvolatile Memory Technologies” Nanaoscale Res Lett., 9(1), 2014. [2] H. Jayakumar et al., “Powering the Internet of Things” IEEE/ACM Int. Symp. On Low Pow. Elec. Desgn. (ISLPED), 2014. [3] J. M. Portal et al., “An overview of non-volatile flip-flops based on emerging memory technologies,” J. Electron. Sci. Tech., 12(2), 2014. [4] S Bhatti, et al., "Spintronics based random access memory: A review", Mater. Today, vol. 20, pp. 530-548, 2017. [5] Y. Xie, J. et al., “From materials to systems: a multiscale analysis of nanomagnetic switching”, Jour. of Comp. Elec., 2017. [6] B. C. Lee, et al., “Phase-Change Technology and the Future of Main Memory”, IEEE Micro, 30(1), 2010. [7] T. Kim et al., "High-performance, cost-effective 2z nm two-deck cross-point memory integrated by self-align scheme for 128 Gb SCM," IEEE International Electron Devices Meeting (IEDM), 2018. [8] Y. Ye, et al., “A non-volatile flip-flop based on diode-selected PCM for ultra-low power systems”, Proceedings of SPIE, 9818, 2016. [9] C. Xu, et al., “Overcoming the challenges of crossbar resistive memory architectures”, Int. Symp. on High Perf. Comp. Arch. (HPCA), 2015. [10] H. Wu et al., "Device and circuit optimization of RRAM for neuromorphic computing," in IEEE IEDM, 2017, pp. 11.5.1-11.5.4. [11] A. Sheikholeslami et al., “A Survey of Circuit Innovations in Ferroelectric Random-Access Memories” Proc. to the IEEE, 2000. [12] H. Kimura et al., “A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability,” IEEE A. S.S Cir. Conf., 2014, [13] J. Müller, et al., “Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG,” in IEEE VLSI Tech. Dig., 2012. [14] Sumitha George, et al., “Non-volatile Memory Design Based on Ferroelectric FETs”, Desgn. Auto. Conf. (DAC), 2016. [15] S. K. Gupta, et al., “Harnessing ferroelectrics for non-volatile memories and logic”, Int. Symp. On Qual. Elec. Desgn., 2017. [16] S. George, et al., “Symmetric 2-D-Memory Access to Multidimensional Data” IEEE Transactions on VLSI, 26(6), 2018. [17] X. Li et al., “Enabling energy-efficient nonvolatile computing with negative capacitance FET,” IEEE Trans. on Elec. Dev (TED)., 2017. [18] K. Ni, et al., “SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications” Int. Elec. Dev. Meet. (IEDM), 2018. [19] S. K. Thirumala et al., “Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications” in Dev. Res. Conf., 2018. [20] S. K. Thirumala et al., “Reconfigurable Ferroelectric Transistor--Part I: Device Design and Operation”, IEEE Trans. On Elec. Devices, 2019. [21] S. K. Thirumala et al., “Reconfigurable Ferroelectric Transistor-Part II: Application in Low Power Non-Volatile Memories”, IEEE Trans. On Electron Devices, 2019. [22] S. K. Thirumala, et al., “Dual Mode Ferroelectric Transistor Based Non-Volatile Flip-Flops for Intermittently-Powered Systems”, Int. Symposium On Low Power Electronics And Design, 2018. [23] A. Aziz, et al., "Physics-Based CircuitCompatible SPICE Model for Ferroelectric Transistors", IEEE Elec. Dev. Let. (EDL), 37(6), 2016. [24] M. Kobayashi, et al., “Experimental study on polarization-limited operation speed of negative capacitance FET with ferroelectric HfO2”, IEEE Int. Elec. Dev. Meeting (IEDM), 2016. [25] Shu-Yau Wu, "A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor," in IEEE TED, 21(8), 1974. [26] Z. Krivokapic, et al., “14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications” IEEE Int. Elec. Dev. Met. (IEDM), 2017. https://www.mosis.com/files/scmos/scmos.pdf
Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - This paper presents an overview of the operation and applications of reconfigurable ferroelectric transistors (R-FEFETs) which offer unique logic-memory coupling in the device characteristics leading to novel circuit design possibilities. R-FEFETs feature dynamic reconfiguration between (a) volatile mode for logic operations and (b) nonvolatile mode for memory operation. An R-FEFET consists of two FE stacks which interact with each other and a common underlying transistor, to enable run-time tuning of hysteresis and the aforementioned reconfigurability. We discuss how such novel features of R-FEFETs can be utilized to design energy-efficient non-volatile memory (NVM) and non-volatile flip-flop (NVFF) designs. For NVMs, read-write conflicts can be effectively mitigated. In particular, R-FEFETs based 3T NVM exhibit significant advantage over existing standard FEFET based NVM design with 55% lower write power and 37-72% lower read power at iso-access time. R-FEFET based NVFFs offer the design options of an auto-backup (RNVFF-1) without the need of any additional circuitry/back-up control signals, or on-demand backup (RNVFF-2) with lower normal operational energy over RNVFF-1. Compared to an FEFET based NVFF, RNVFF-1 achieves 47% lower check-pointing energy, with a penalty of 6% in operation energy. RNVFF-2 shows 30% lower check-pointing energy with similar operation energy. At the system level, the RNVFFs achieve 25-33% register-level energy savings, in a state-of-the-art intermittently powered platform.
AB - This paper presents an overview of the operation and applications of reconfigurable ferroelectric transistors (R-FEFETs) which offer unique logic-memory coupling in the device characteristics leading to novel circuit design possibilities. R-FEFETs feature dynamic reconfiguration between (a) volatile mode for logic operations and (b) nonvolatile mode for memory operation. An R-FEFET consists of two FE stacks which interact with each other and a common underlying transistor, to enable run-time tuning of hysteresis and the aforementioned reconfigurability. We discuss how such novel features of R-FEFETs can be utilized to design energy-efficient non-volatile memory (NVM) and non-volatile flip-flop (NVFF) designs. For NVMs, read-write conflicts can be effectively mitigated. In particular, R-FEFETs based 3T NVM exhibit significant advantage over existing standard FEFET based NVM design with 55% lower write power and 37-72% lower read power at iso-access time. R-FEFET based NVFFs offer the design options of an auto-backup (RNVFF-1) without the need of any additional circuitry/back-up control signals, or on-demand backup (RNVFF-2) with lower normal operational energy over RNVFF-1. Compared to an FEFET based NVFF, RNVFF-1 achieves 47% lower check-pointing energy, with a penalty of 6% in operation energy. RNVFF-2 shows 30% lower check-pointing energy with similar operation energy. At the system level, the RNVFFs achieve 25-33% register-level energy savings, in a state-of-the-art intermittently powered platform.
UR - http://www.scopus.com/inward/record.url?scp=85084948306&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85084948306&partnerID=8YFLogxK
U2 - 10.1109/NANOARCH47378.2019.181302
DO - 10.1109/NANOARCH47378.2019.181302
M3 - Conference contribution
AN - SCOPUS:85084948306
T3 - NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
BT - NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019
Y2 - 17 July 2019 through 19 July 2019
ER -