Numerical study of reduced contact resistance via nanoscale topography at metal/semiconductor interfaces

Reduction in contact size via scaling leads to an increase in parasitic contact resistance, which can be a limiting factor in aggressively scaled high-frequency transistors. Using numerical modelling, we predict that nanoscale topography at the metal/semiconductor interface can reduce the effective specific contact resistance by 25% or more using features 10 nm or less in width, even for doping densities as high as 10²⁰ cm^-3. Previous studies have shown that these features cause an increase in tunnelling current for lightly doped semiconductors. However, we have found that for heavy doping or low barrier heights, the main factor reducing contact resistance is increased interfacial area.