@inproceedings{a3d6fac417424b5ebf4a0a2a717040db,
title = "On reconfigurable single-electron transistor arrays synthesis using reordering techniques",
abstract = "Power consumption has become one of the primary challenges in meeting Moore's law. Fortunately, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption during operation. An automated mapping approach for the SET architecture has been proposed recently for facilitating design realization. In this paper, we propose an enhanced approach consisting of variable reordering, product term reordering, and mapping constraint relaxation techniques to minimizing the area of mapped SET arrays. The experimental results show that our enhanced approach, on average, saves 40% in area and 17% in mapping time compared to the state-of-the-art approach for a set of MCNC and IWLS 2005 benchmarks.",
author = "Chiang, {Chang En} and Tang, {Li Fu} and Wang, {Chun Yao} and Huang, {Ching Yi} and Chen, {Yung Chih} and Suman Datta and Vijaykrishnan Narayanan",
year = "2013",
doi = "10.7873/date.2013.362",
language = "English (US)",
isbn = "9783981537000",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1807--1812",
booktitle = "Proceedings - Design, Automation and Test in Europe, DATE 2013",
address = "United States",
note = "16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conference date: 18-03-2013 Through 22-03-2013",
}